The subject application is directed generally to the art of synchronous digital circuitry, and more particularly to synchronous digital circuitry in which a lessened effect of electromagnetic interference (“EMI”) is desirable.
Most digital devices today operate synchronously. That is, data processing operations occur under a timing dictated by a digital clock signal. Such digital clock signals are typically square waves that oscillate at a selected frequency. As improvements are made to digital processing devices, clock frequencies may be increased. Faster clock frequencies allow for improved data processing throughput. Current digital clock frequencies are already in the multi-gigahertz range. As clock frequencies continue to rise, an increased incidence of electromagnetic interference exists. Such EMI requires that special shielding or casing be developed to dampen such interference. EMI can cause data errors in associated data processing devices, as well as provide for radio frequency (“RF”) interference for analog devices such as radios and televisions.
Designers have become aware that implementing a spread spectrum clock generator (“SSCG”) works to substantially reduce the high energy spikes associated with digitally-generated EMI.
SSCG circuitry functions to vary slightly a frequency of a digital clock signal over time. This is accomplished by reducing “noise” associated with harmonics of a large scale integration (“LSI”) clock signal. SSCG circuitry functions to alter slightly a signal interval and thus diffuses a frequency spectrum and lowers a peak value.
A side effect from the use of an SSCG is an introduction of a slight jitter in the system clock. However, such jitter is generally of little consequence other than in particular applications relating to communication network interfaces or input/output interfaces, as well as other applications having varying tolerance to jitter. Thus, it is desirable to be able to vary a degree of frequency shift and associated jitter to accommodate a lessening of peak EMI while simultaneously minimizing the jitter to acceptable application parameters.
Current SSCG circuitry employs frequency comparators and voltage controlled oscillators (“VCO”) to accomplish the shifting of frequency to result in a modulated clock signal. While effective, such analog-based implementations render it difficult and expensive to accomplish an SSCG circuitry, particularly in applications when a system is desired to coexist on other standard digital circuitry and in conjunction with a single substrate.
The subject invention provides for a digital spread spectrum clock generator which accomplishes selected frequency variation of an associated digital clock while minimizing the required use of extensive or incompatible analog circuitry.